Emerging Technologies Papers

ALT Hollow-Core Fiber (HCF) is emerging as a disruptive technology for next-generation optical networks, offering 30% lower propagation latency than standard Single-Mode Fiber (SMF), record-low attenuation (0.05-0.1 dB/km), and nonlinearities reduced by three to four orders of magnitude. While the physical-layer benefits of HCF have been extensively demonstrated, recent industrial commitments by hyperscalers (e.g., Microsoft, Amazon) and the rapid maturation of nested antiresonant nodeless fibers (NANF) call for a systematic assessment of the impact of HCF at the network level. Building on a series of prior contributions, we overview four emerging network-wide use cases for the selective deployment of HCF in hybrid SMF/HCF networks: (i) latency-constrained Edge Data Center (edgeDC) consolidation; (ii) energy-efficient high-power amplification; (iii) capacity scaling via single-fiber bidirectional (BiDi) transmission; and (iv) coexistence of classical and quantum (QKD) channels. Consolidate

ALT Muscle stiffness is a physiologically meaningful biomarker associated with a wide range of musculoskeletal and neurological conditions. However, existing muscle stiffness assessment methods, such as shear wave elastography (SWE), manual palpation, and handheld mechanical probes, remain impractical for continuous, everyday monitoring due to bulky hardware, operator dependence, and limited self-use. Meanwhile, wearable muscle-sensing modalities such as Electromyography (EMG) and Mechanomyography (MMG) primarily capture muscle activation rather than passive mechanical properties of tissue at rest, leaving a critical gap in portable monitoring of resting muscle stiffness. In this work, we present WAVES, a wearable system for continuous monitoring of muscle stiffness via active vibroacoustic sensing. WAVES injects controlled vibroacoustic excitation into soft tissue and estimates muscle stiffness by measuring shear-wave propagation velocity through Time-Difference-of-Arrival (TDoA) analysis

ALT We propose an algorithm that can synthesize circuits to gate sets consisting of a 2n-arity Clifford gate and arbitrary single qubit rotations. To do this, we represent the circuit as a sequence of Pauli gadgets and jointly synthesize them by placing the multi-qubit Clifford in the synthesized circuit and pushing its adjoint through the remaining gadgets such that some qubits are disconnected from some gadgets. The pushed gadgets are collected in a Clifford tableau, which is decomposed afterwards. With the help of our algorithm we run experiments where we synthesize circuits to varying sizes of target multi-qubit gates. These experiments indicate that increases in gate size can lead to smaller output circuits, and that different connectivity constraints have meaningful differences in how higher arity gates effect the circuit sized.

ALT Prototyping and early-stage circuit evaluation for emerging transistor technologies require fast and accurate compact models for SPICE simulations. Standard physics-based compact models, such as BSIM, offer high fidelity but demand extensive domain expertise and time-consuming equation formulation for every new physical effect, significantly slowing technology development. Neural network (NN)-based models offer a scalable alternative approach, but they rely heavily on smooth numerical solver data with explicit high-order derivative information. However, measurement data suffers from complex noise patterns, making derivative extraction challenging and complicating NN-based transistor modeling. This work presents a derivative-free NN training framework employing spectral normalization to naturally smooth derivative behavior and filter measurement noise. Using drain current measurements from a fabricated 28 nm ferroelectric device, we design an NN-based compact model that captures the ful

ALT Many neuromorphic systems possess rich internal computational structures shaped by their physical dynamics. However, existing metrics characterize only global computation, leaving these local structures unresolved despite their importance for system interpretation, optimization and miniaturization. Here, we introduce local information processing capacity (L-IPC), which represents individual dynamical states as vectors in an infinite-dimensional Hilbert space and decomposes their computational properties through subspace projections onto nonlinearity orders and memory steps, with the residual quantifying computational irrelevance. Applied to three systems with comparable global capacities (an echo state network, an ion-gating reservoir and a spin-wave reservoir), L-IPC reveals markedly different distributions of computation, ranging from homogeneous to spatially, temporally and spectrally structured patterns. These local profiles further guide task-specific pruning, outperforming standa

ALT Rapid Single Flux Quantum (RSFQ) logic can operate at ultra-high clock frequencies; however, its physical design is complicated by explicit splitter trees and deep gate-level pipelines in which every logic gate is clocked. To address this challenge, we present qLevelPlace, a level-based placement framework for RSFQ circuits. We separate gate and splitter placement into two stages to better support levelguided gate-to-row assignment and use a timing-aware quadratic cost function to penalize long interconnects. Experiments on the benchmark circuits show that, on average, qLevelPlace achieves a 2.65× higher clock frequency and a 51% reduction in layout area compared with the state-of-the-art RSFQ placer qPlace.

ALT Future molecular communication (MC) networks are envisioned to use the human cardiovascular system as a channel. Disease-related changes affect particle transport, allowing an MC receiver to also act as a sensor. In this work, we investigate plaque formation in a carotid bifurcation through a systematic fluid-dynamics simulation study with non-Newtonian blood rheology. We analyze how plaque geometry changes branch-specific particle reception and timing, and use these observations to estimate plaque-induced channel obstruction. At an illustrative reference of only 128 emitted particles, a 250 ms observation window and 50 ms temporal resolution, a Ridge detector estimates maximum local channel-width reduction with a mean absolute error of 8.30 percentage points. We evaluate robustness across system constraints like particle budgets, observation windows, branch access, detection efficiency, count resolution, and synchronization. Coarse counting has little effect when timing features remai

ALT Morphogenesis of diatom silica shells involves a sequence of topological transitions: initially separate ribs grow and branch, then merge through bridges, leaving a regular network of pores. Existing models based on diffusion-limited aggregation or reaction-diffusion reproduce either branching or pore formation, but not both within a single framework. Here we propose a two-stage model of diffusion-driven morphogenesis with evolving connectivity. The model is formulated on a fixed finite element mesh with a density field on an active layer. Stage 1 reproduces dendritic growth, where a stimulus based on the local diffusive flux exceeds a threshold. Stage 2 uses an inverted stimulus, where high local flux suppresses precipitation, stabilizing pores between the dendrites. The update rules are analogous to sensitivity in density-based topology optimization and to strain energy density in bone remodeling. The model predicts distinct morphological regimes on each stage, controlled by the resp

ALT The electronic structure of molecules is foundational for scientific advancement, however determining it remains challenging due to the growth of the molecular Hilbert space with system size. Recent approaches address this by using quantum circuits to sample candidate configurations and sample-based quantum diagonalization (SQD) to compute the ground state. We propose ZenKO, a novel gradient-based, iterative SQD method that employs a hybrid quantum-classical approach. ZenKO decomposes configuration selection into discovery, validation, and refinement, enabling targeted subspace expansion and guided exploration. Our evaluation demonstrates that, across H₂O, H₁₀, and N₂ molecules, ZenKO improves ground-state accuracy compared to prior iterative methods, while significantly reducing classical cost.

ALT The increasing diversity and computational demands of automotive edge functions require hardware architectures that support heterogeneous processing while limiting implementation complexity and system overhead. We investigate a system-level approach in which a common, fixed photonic front end provides a shared physical transformation for multiple processing functions, while application adaptation is handled by lightweight peripheral processing. We propose the Versatile Photonic Encoding Platform (VPEP), implemented using a fabricated silicon-photonic chip with 32 phase-modulated inputs, a passive fixed encoding core, and 17 on-chip photodetector outputs. Without reconfiguring the photonic core, the same chip is evaluated across four representative functions relevant to automotive edge systems: classification and regression for machine learning, analog-to-digital conversion for mixed-signal processing, and photonic information encoding and recovery for communication-related processing.

ALT Speculative decoding speeds up large language model (LLM) serving only while the GPU has spare compute, so the best draft length, the number of tokens a small drafter guesses per step, shrinks as the batch grows. vLLM lets operators set the draft length for each batch size with a hand-written table, but nothing measures or corrects that table. We present TableTune. Its tuner times the decoding step for every batch size and draft length on vLLM's own serving path and computes, in minutes, the table that maximizes throughput. Its controller, a vLLM plugin, tracks how many guesses are accepted in live traffic and rebuilds the table while serving. We measure TableTune only against other ways to speculate. On an H100, the tuned table delivers at least 94% of the throughput of the best fixed draft length at every load in four of five drafter settings (88% in the fifth) without the operator having to know which length that is. Against reimplementations of TurboSpec- and Nightjar-style control

ALT Single-photon avalanche diodes (SPADs) are essential components of quantum communication receivers. In practical systems, some SPADs exhibit intrinsic step-like changes in dark-count rate (DCR), commonly referred to as random telegraph signal (RTS) noise. Similar RTS-like variations, however, can also arise from stray light, temperature-dependent threshold crossings, cable disturbances, electrical interference, and other readout artifacts. Distinguishing intrinsic RTS from these artifacts is important because they originate from different mechanisms and require different corrective actions. We present a self-referenced diagnostic that primarily uses the low-to-high afterpulse-yield ratio R, together with complementary checks based on DCR-state reproducibility, cross-channel behavior, and event timing. Four commercial SPAD modules were monitored in darkness for more than 920 h. Three exhibited intrinsic DCR switching of 44.59%, 19.33%, and 2.77%, with corresponding R values of 0.9996±0.

ALT Field applications in chemical sensing, from portable safety monitors to mobile robots, require models that are lightweight, fast to respond, and can be recalibrated from limited labelled data. Current gas classification pipelines assume controlled sampling cycles and offline feature extraction, and rely on computationally expensive models. With a few thousand neurons and sub-milliwatt power consumption, insects reliably classify odours in open environments. Inspired by the insect olfactory system, we present a neural network architecture that classifies raw sensor array readings using a sparse, high-dimensional binary representation. We evaluate it on random sequences of single gases and binary mixtures, introducing new samples dynamically and classifying gas identity from the transient sensor response. In this setting, the architecture out-performs a linear svm on gas mixtures and matches an optimised non-linear svm, while maintaining online class-level frequency estimates that disti

ALT Physical neural networks (PNNs) leverage device physics in electronics, optics, and related domains to enable energy-efficient neural networks. Broken-isomorphism PNNs replace linear operations with multivariate physical transformations, modifying how input signals are mapped to device variables. We exploit network architectures emerging from these mappings by treating the routing between signals and input variables of physical devices as trainable parameters. This approach expands device-level tunability of the physical transformations while, at the system level, demonstrating improved expressivity of PNNs with negligible additional inference overhead. This discrete routing is optimized by training a categorical distribution using Gumbel-Softmax reparametrization. We evaluate this approach using experimentally calibrated differentiable models of multivariate electronic RNPUs for MNIST and CIFAR-10 classification. Using variable selection, we improve the MNIST classification accuracy f

ALT Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a 3nm nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we a

ALT Analog in-memory computing delivers efficient neural network inference at the edge, but systems deployed in non-stationary environments may need to adapt in situ to locally acquired data. Backpropagation faces two structural obstacles here. Its global error transport lets stochastic write errors compound across layers, and its backward pass demands bidirectional, high-precision peripheral circuitry absent from inference-oriented crossbar arrays. We introduce Channel-wise Spatial Gradient learning (CwSG), a strictly local, forward-only rule that trains each convolutional layer by rewarding spatial variation in its feature maps. In simulations replaying the measured trajectories of 1,189 phase-change memory and 1,268 filamentary memristor devices, CwSG learns with single, unverified, sub-1 V pulses. It matches backpropagation on phase-change memory with 59-fold fewer pulses and outperforms it by 53 percentage points on highly variable filamentary memristors, with 8-bit forward converters

ALT Neuro-symbolic artificial intelligence (NeSy AI) combines neural perception with symbolic reasoning, enabling logical reasoning. Hyperdimensional computing (HDC) is promising for NeSy AI, owing to its high parallelism and strong robustness to noise. However, the dense neural operations and memory-intensive symbolic inference in NeSy impose a severe "memory wall" bottleneck. Existing NeSy accelerators either focus solely on symbolic kernels or rely on conventional digital architectures, lacking a unified and energy-efficient hardware substrate. Moreover, exploring optimal hardware design configurations often requires costly trial-and-error. In this work, we propose UnO-NeSy, a unified CiM framework for optimizing NeSy computing. UnO-NeSy consists of UnO-CiM, an ultra-low-power NeSy architecture based on a homogeneous 2FeFET–2R compute-in-memory (CiM) array that supports both neural computation and HDC reasoning, and UnO-Sim, a cross-workload, end-to-end CiM simulator that models device

ALT On ranked directed acyclic graphs coupled by vertex conflicts we study exact-arrival multi-agent path finding (departure and arrival pinned in place and time) posed as a distributed output task: every cell must emit its own bit of a valid joint path-support mask. The machines are cellular: one automaton per cell, state factored over cells, communication only along a fixed local fabric, synchronous rounds, a query-independent output round, no central decoder, and a per-topology transition code. "Necessary" here means: on an explicit hard topology, over all its feasible queries, no universally correct local-only architecture can renounce either temporal orientation; with global flags, impossibility becomes a bandwidth-round trade-off. The class is not vacuous: a flooding machine solves every instance in as many rounds as the diameter of the local fabric. The bound survives two concessions: we supply every agent's exact individual cavity, which alone solves the single-agent problem in zer

ALT The growing memory demands of artificial neural networks pose a major challenge for energy-efficient computing, particularly for models that rely on large collections of high-dimensional weight and embedding vectors. Conventional memory architectures store these vectors individually, requiring many memory cells per vector and limiting achievable storage density. Here we demonstrate an analog memory architecture that encodes multiple vectors in a distributed superposition within a single memory array. Individual vectors are recovered through in-memory matrix-vector multiplication, allowing the degree of superposition to be tuned to balance storage density against recall fidelity. This approach introduces a new scaling dimension for analog memory, in which effective storage density can be increased without a corresponding increase in the number of physical memory cells. The distributed representation also provides resilience to device-level noise. We implement the architecture on a proto

ALT Distributing quantum circuits across a network of quantum devices is a recent approach to improve the scalability of quantum computation. Entangled pairs of qubits distributed across network nodes are used as a communication resource for executing inter-node (remote) gates. However, establishing these entanglement pairs incurs significant latency, and doing so during the circuit's execution may lead to the decoherence of logical qubits. Instead, it may be beneficial to distribute certain entanglement pairs before the circuit is executed. Thus, we consider the problem of distributing a quantum circuit across a quantum network containing some pre-distributed entanglement pairs and seek to minimize the execution time of the circuit. We address this problem in three steps. First, given the quantum network and (optionally) a probability distribution over training circuits, we determine a set of pre-distributed entanglement pairs under a specified budget. Second, we compute a qubit-to-memory