@CamelCdr

🐘 @camelcdr@tech.lgbt

Joined March 2024
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  • Followers286
89Media
lol, Akeana another one
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Nothing but the truth. Credit to u/Substantial_Help_722 for the first four tiles.
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TLDR: 3R1W ISA with memory operands, 32-bit instructions, no flags, lots of predication, many instruction variants, the regular set of bitmanip instruction with inverse variants, compare-and-branch Vector: CSR selectable VLEN 128/256/512/1024bit, masking, but no element wise VL
Tachyum@TachyumAug 12
Tachyum Open Sources its Prodigy ISA and Platform to Make AI Available to Everybody in the World tachyum.com/media/press-rele…
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forgot to mention the register windows
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I didn't look at the FP/complex and transactional memory part. At first glance, if it wasn't for memory operands, the rest seems fine. While not VL predicated, the vector part supports VLA programming, though essentially using the same encoding for all vector lengths.
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Now if only there was hardware and a serious company behind it...
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On some better news RVV element-wise pext/pdep proposal 🎉 github.com/riscv/riscv-isa-m…

Zvbext: element-wise bit compression and expansion by wangpc-pp · Pull Request #3296 · riscv/risc...

Zvbext provides VBCOMPRESS.VV/VX and VBEXPAND.VV/VX for rearranging bits independently within each vector element. VBCOMPRESS gathers the bits selected by a selection mask into contiguous least-sig...

github.com
@fclc cmp lea char@FelixCLC_Aug 10
Having a Normal reaction to a newly proposed instruction
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g = ~m & ~even; g |= g >> 1; p = m & even; p |= p << 1 | g; s = (g+p+start^g^p) & even | start; return s | (m&s^even)<<1;
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constant time floating point operations
Longhorn@never_releasedJun 24
commutative floating point operations
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I feel like overlapping FP and integer physical register file and ports may be better than overlapping FP with SIMD. Because scalar FP needs higher issue and lower latency than SIMD FP.
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If you have 128-bit SIMD the goals are mostly aligned, but for >=256-bit sharing FP with SIMD becomes less attractive in my mind. This also isn't all that relevant if your integer execution isn't something like 6 wide or wider.
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yes, this is good, more of that please This is a lot better than the alternative of a bunch of people crating their own incompatible subsets.
Pete Cawley@corsixMay 20
Someone looked at the overlapping mess of AVX512 extensions and thought “yes, that is good, more of that please”
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Replying to @FelixCLC_
@FelixCLC_ I tested the impact of disabling RVC on the SpacemiT X100 4-wide OoO core with clang. Enabling RVC resulted in a roughly 10% performance improvement. Not sure what this actually tells us about RVC exactly, but it's certainly interesting.
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The L1I bandwidth of the X100 is 16-bytes / cycle, so it should be able to feed the 4-wide core without compressed instruction. While the X100 supports a handful of fusion pairs, those aren't compressed only. (bitwise+bitwise, mul+add, add+load/store, slli+sr*i)
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camel-cdr retweeted
Andreas Abel@uops_infoMar 29
I have added latency, throughput, and port usage data for Emerald Rapids, Meteor Lake, Arrow Lake, and Zen 5 to uops.info/table.html.
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The RVP spec is coming along: github.com/riscv/riscv-p-spe… Here is a untested implementation of JPEG upsample in RVP: godbolt.org/z/r5bGGPsj5 This uses the current draft intrinsics. With the overloaded ones this will be less verbose. __riscv_preinterpret is still way to long IMO.
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Replying to @FUZxxl
@FUZxxl A similar idea to the fast-path branch: s1first rd, rs1, rs2 Sets rd to 1 if rd1 becomes ready first, or 0 if rd2 becomes ready first, the other depenendcy is discarded.
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This allows you to dynamically load ballance different code paths, which can be especially usefull if you have a parallel problem and you want to process the elements with SIMD bit one or two simultaniously with scalar.
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The problem with mixing scalar and SIMD today, is that you need to be conservative with the number of scalar elements processee, because if the scalar iteration is slower than the SIMD one, the SIMD has to wait. With s1first you wouldn't have to wait, if one path is faster.
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gist.github.com/camel-cdr/bd…

Visualizing the RISC-V Instruction Set

Visualizing the RISC-V Instruction Set. GitHub Gist: instantly share code, notes, and snippets.

gist.github.com
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here are some unratified extensions: * red: Zibi (branch immediate) * green: additional V extensions (zvabd, zvzip, various dot product things) * blue: current IME and SiFive AME proposal * yellow: P proposal This uses a slightly different bit order.
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