Muxim (@Meito_1) profile picture
Joined December 2020
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The most unexpected and pleasant part of switching from an iPhone XS to the iPhone 17 is the 8 GB of RAM. It’s really nice that a YouTube video is still there after spending some time browsing
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When i bougt my pc the upgrade was huge, but arguably the biggest upgrade was going from 5400rpm HDD to Gen4 SSD. Now to get the same level of storage upgrade i would probably need to wait a decade
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How is this possible? source: youtube.com/watch?v=nc7MHEMc…
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Per optimum it is glossy coating
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RDNA5 is expected to include dedicated matrix cores RDNA4 added BVH8 but in software with intersections running on a dedicated hardware, RDNA 5 will have a new Radiance Cores which should handle BVH I think RDNA5 CU will be structurally similar to Ada youtu.be/1LCMzw-_dMw?t=290
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At this point, I guess I’ll just have to accept the fact that I’ll never be able to use a modern phone as comfortable as the X/XS ever again. The biggest markets are 6.3” and 6.9”, smaller market in the middle and foldable, miserable market for below 6.3” youtu.be/nvW9aXvSyY4?si=ci5E…
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Condolences to mini users, this how “compact modern phone”(IPhone 17) looks next to it
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I’m a happy man
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My expectations for Zen 6 and Top RDNA5 sku CPU: 10% IPC + 10% clocks, 8000 DDR5 1:1, ~4000 ST Geekbench 6 GPU: 80-96CU, 256bit, 24GB of memory(3GB GDDR7 chips), 40-50% over 9070XT My opinion on this product will be based on whether they can hit, exceed or miss this expectations
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One day desktop will be respected and we will be getting this kind of previews about the next gen product performance long in advanced too 🤓
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This looks like 36MB of L3 cache, but i thought it would take less space. I would expect 48MB to take as much space as 12 cores I think Zen 6 would benifit more from a bigger L1 instruction cache(48KB or 64KB)
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Both undervolting and overclocking seem like a valid option
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Appreciation to @Faintmaster post. I hope UDNA breaks this trend, we don't need another Blackweel
AMD reversed engineered Pascal = RDNA (WGP/dual CU, wave32, way higher clocks, better memory compression) Turing = RDNA2 (RT, mesh shader) Ampere = RDNA3 (bigger registers, dual FP32, TC3 tho kinda delayed because original is from Volta/Turing) Ada = RDNA4 (BVH8, SER, FP8)
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Finally, for a moment i thought we are not going to get some outlandish shit this time. But now i can sleep in peace
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I'm interested in making a prediction just to see how it ages. Rubin desktop. Only 202 increased TPC to 8 per GPC. I expect this for every SKU in the next generation. 202: 14*8 = 224SM or 16*8 = 256SM 203: 7*8 256-bit = 112SM 205: 5*8 192-bit = 80SM
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202: 384-bit 36G 203: 256-bit 24G 205: 192-bit 18G
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