@ ETH Zurich. Zurich based Austrian expat. He/him.
Zurich, Switzerland
Joined March 2009
- Tweets137
- Following540
- Followers348
- Likes1.2K
Florian Zaruba retweeted
There is an alternate reality where Cray took their vector supercomputers, ditched FP64 calculations, and went with one FP32 pipe and a BF16 tensor core pipe. The same instruction set, memory architecture, and vector registers would have made a sweet deep learning machine, in many ways nicer than SIMT CUDA programming on GPUs. A Y-MP class machine like that could have delivered the AlexNet and DQN moments two decades earlier.
Even doing everything in FP64 with no architectural changes, a Cray-1 would have been the best machine in the world for neural networks. If @geoffreyhinton had access to one for early research, the case could have been made for the architectural modifications to 10x the performance.
Florian Zaruba retweeted
🌟We have had an amazing time at #RISCVSummitEurope so far! Watch #RISCV Ambassador @FlorianWoh's #recap video, highlighting a few of the incredible Summit announcements, sessions, and activities. We can't wait to see everyone for another packed day tomorrow! #RISCVeverywhere
Florian Zaruba retweeted
In order to put to rest incorrect information that recently appeared on social media and several more prominent websites, we have published a summary of our project Occamy: pulp-platform.org/occamy/
Florian Zaruba retweeted
Cool @AxeleraAI booth at #ew23 looks great.
#AI made in Europe
And they use #RISCV in some chips
Greetings to the #RISCVambassador @be4web
Florian Zaruba retweeted
We’re thrilled to share that we have closed our $27million Series A and are ready to launch our AI acceleration platform in early 2023! axelera.ai/european-ai-start…
#deeptech #ai #ml #edgeai
Florian Zaruba retweeted
Hello (ex) @pulp_platform's Ariane/@openhwgroup's CVA6!
Thanks to Massimiliano.G's LiteX port, it's possible to regain some freedom:
- No longer restricted to Xilinx/Genesys2/MIG.
- New peripherals to play with :)
- 100% open-source SoC!
- ...
Try it: litex_sim --cpu-type=cva6
Florian Zaruba retweeted
This is great! That's what I am talking about when I push for open hardware!! Avalanche effect 🚀😎
Thanks @LucaBeniniZhFe ! We are also open-sourcing the code following the same principles as the @pulp_platform and the @openhwgroup here: github.com/artecs-group/PERC…
Florian Zaruba retweeted
We are delighted to see our Ariane helping researchers at Google 😇. Learn more in the article "Google Deploys AI to Build Better AI Hardware Accelerators".
extremetech.com/extreme/3236…
Florian Zaruba retweeted
Can you design a chip in GF22 with 10 RISC-V cores in 5 weeks @fabianschuiki @be4web? Challenge accepted, hold our beers for a while. We present Thestral, PULP chip Nr. 38 taped out. But be careful - only people that have seen death can see a Thestral.🤣😼
asic.ethz.ch/2020/Thestral.h…
Florian Zaruba retweeted
The @hotchipsorg virtual conference is around the corner – are you ready? Join #RISCV members @AlibabaGroup and @ETH_en with @pulp_platform from Aug. 16 – 18 to learn more about RISC-V's potential for application development and chiplet architecture. buff.ly/3gOSCn8
Florian Zaruba retweeted
We would like to share with you our new paper. Nils has been collecting data by running programs on Ariane on FPGA for weeks to generate these graphs 😅.
Read more on what he has been doing on Prevention of Microarchitectural Covert Channels at arxiv.org/abs/2005.02193
Florian Zaruba retweeted
Open-Source Hardware, but a Proprietary Design Language?!
LLHD.io thinks this is not right!
Check out our PLDI paper: arxiv.org/abs/2004.03494
@pulp_platform, @CSatETH, @spcl_eth, @lowRISC, @fabianschuiki, #riscv
Florian Zaruba retweeted
Among RISC-V leaders in #ecosystem we welcome RISC-V #trace & #debug standard. Congrats who contributed & back new standard @Andes_Tech @Codasip @EsperantoTech @ETH_en @ImperasSoftware @MicrochipTech @openhwgroup @Seagate @SiFive @syntacore @westerndigital riscv.org/2020/03/risc-v-fou…
Florian Zaruba retweeted
As ASPLOS 2020 Lausanne got cancelled, we are sharing with you @JBalkind's video with slides on 'BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research'...Ariane Inside 😃
parallel.princeton.edu/paper…
youtube.com/watch?v=iQKkSgUG…
Florian Zaruba retweeted
In this paper is presented Snitch: A #RISCV processor tuned for the highest possible energy efficiency on DP floating-point arithmetic, which provide both SSR and FREP extensions and achieving 3.5x more energy efficiency that state-of-the-art systems.
arxiv.org/pdf/2002.10143.pdf
Florian Zaruba retweeted
Fresh from Jeff Dean's ISSCC plenary talk... Guess which open source core is Google using to benchmarks their AI-driven IC placement engine?
Florian Zaruba retweeted
Researchers have proposed Stream Semantic Registers: A lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating a large number of loads/stores. #RISCV
arxiv.org/pdf/1911.08356.pdf
Florian Zaruba retweeted
An @ETH_en team led by Torsten Hoefler is analyzing heat production in transistors to help inform new semiconductor designs. The team is a Gordon Bell finalist for its recent work on Summit. Read more: bit.ly/33wlrOD
Florian Zaruba retweeted
Join us for our @OpenPiton tutorial on Oct 12th (afternoon) at MICRO 2019! We'll teach you how to get research done using OpenPiton with Ariane RISC-V cores from @pulp_platform running on Amazon F1. @MicroArchConf openpiton.org/MICRO19_tutori…
Florian Zaruba retweeted
Giving an overview of the @pulp_platform, our cores, platforms, and systems, our involvement in the @risc_v ecosystem, and a cross section of our research and chip activities at #HotChips31!
Now a front-of-house view of Fabian presenting @pulp_platform @risc_v open-source cores at the @hotchipsorg tutorial
