We present "Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency" spanning the monitoring granularity and area trade-off through three variants. See how it performed in GF 12nm: arxiv.org/pdf/2608.30435 @chaoqun_L

Congratulation to Enrico and the entire team at ETH Zurich on winning the 2026 Hot Chips Best Student Poster Award

Christoph & Marco open-sourced their IEEE CEEUS workshop "Anatomy of a Wearable Ultrasound System" doi.org/10.5281/zenodo.21030…. Free to reuse for teaching or projects, find the repo with student version & teacher's notebook with solutions running in Colab here github.com/luuleitner/anatom…

The SwissChips Annual Event took place yesterday at #EPFL Lausanne with members exchanging ideas and discussing the latest developments in chip design and microelectronics. We were there, of course, with Charlie The Bear to chip in!

RISC-V compute nodes are closing the gap with their competitors in the HPC segment! Check out our collaborative paper "Monte Cimone v3: Where RISC-V Stands in High-Performance Computing" arxiv.org/pdf/2605.22831

#DATE2026 is in full swing in Verona! Charlie The Bear is, of course attending, together with our Run, Arianna & Viviane. Come by and say hello to Charlie and our team.

We present "TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link". 910 MHz in 12nm FinFET, up to 1.89 single precision TFLOP/s & 200 GFLOP/s/W. See arxiv.org/pdf/2603.01629 @yichao_zh @MarcoBertuletti

Our #DATE2026 paper "Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores" introduces COPIFTv2 which augments Snitch with lightweight queues for direct, fine-grained communication & sync between integer and FP threads: arxiv.org/pdf/2601.17940

After a bit of delay, we have received back samples from our implementation of the end-to-end open source teaching vehicle Croc github.com/pulp-platform/cro… that serves for our VLSI lecture vlsi.ethz.ch/. Thanks to IHP for supporting this project! asic.ethz.ch/2024/MLEM.html

Our newest design Flamingo has been sent for fabrication. We thank Synopsys for their support to have DDR & PCIe on the chip & the Globalfoundries University Partnership Program to make the tape-out a reality. More info once we had the chance to test it: asic.ethz.ch/2025/Flamingo.h…

NeurIPS 2025's top 50 paper contributors show China and the US neck-and-neck. In the US, corporate labs—Google DeepMind, Meta, Microsoft—now rival top schools like Stanford, CMU, MIT, showing a major shift to industry-led AI research. China’s leaders remain academic: Tsinghua, CAS, Peking, SJTU, HKUST. Singapore (NUS, NTU), Korea (KAIST), UAE (MBZUAI), and Canada (Mila) hold strong. Europe trails, with only Oxford, EPFL, ETH Zurich, and TUM from the EU-27 making the list. --- Source: linkedin. com/posts/pierre-alexandre-balland-20b75b13_who-pushed-the-ai-frontier-at-neurips-2025-activity-7403119036496162817-vRPE

Today we give you another student chip that improves on our example design Croc github.com/pulp-platform/cro…. Here is River which integrates a general-purpose Direct Memory Access engine and a Serial Peripheral Interface controller to enhance I/O capabilities asic.ethz.ch/2025/River.html.

Time to present student chips from this year's VLSI course! 65 students worked in groups of two to improve on our example design Croc github.com/pulp-platform/cro… resulting in 33 designs. 5 made it, supported through the BMBF project. See e.g. Fluffy below asic.ethz.ch/2025/Fluffy.htm…

Greetings from #BioCAS which is currently underway in Abu Dhabi. Here is Sebastian with a "Live Demonstration: Wearable Edge-AI Meets Real-Time Saccadic Eye Movement Classification" using the GAPses smart glasses for a real-time human machine interface.

Here is "CMOS 2.0 - Redefining the Future of Scaling", a joint effort with Imec @imec_int & KIT proposing to revisit the functional scaling paradigm leveraging recent developments in advanced chip manufacturing, i.e. 3D wafer bonding & backside processing arxiv.org/pdf/2510.04535