The following ISA/CPU properties are all independent: - load–store vs. register–memory architecture - fixed width vs. variable width instruction encoding - hardwired vs. microcoded implementation - few vs. many instructions - simpler vs. complex instructions - simple vs. complex addressing modes - weak vs. strong memory ordering - delayed vs. non-delayed branching - windowed vs. flat register file - register-rich vs. register-poor - three-operand vs. two-operand instructions - zero register vs. no zero register - link-register-based vs. stack-based return addresses The properties on the left are historically associated with RISC, while the ones on the right are historically associated with CISC, but they really are independent. Back in the 80s, designing processors based on the properties on the left was advantageous because one could make a faster CPUs at a cheaper cost (at least for the manufacturer, not necessarily for the end user). Back in the late 80s/early 90s, RISC vs. CISC was associated with: - low transistor count vs. high-transistor count - high frequency vs. low frequency Notice how nowadays this association has completely dissapeared. High-performance CPU design can afford bigger transistor budgets and most of the performance of a modern CPU comes from properties completely orthogonal to the ones above.