How can ARM CPUs compete with Intel/AMD when NEON is only 128-bit, while x86 can go all the way to 512-bit with AVX-512? Because 512-bit SIMD does NOT mean 4x the CPU performance of 128-bit SIMD. AArch64 NEON uses fixed 128-bit vectors. AVX2 can use 256-bit vectors, while AVX-512 can use 512-bit vectors. But vector width is only one part of the equation. Performance also depends on: -> How many vector operations can execute in parallel -> Execution throughput and latency -> Clock frequency -> OoO execution -> Cache and memory bandwidth -> How well the workload can actually be vectorized -> Power and thermal limits A CPU with multiple 128-bit execution pipelines can process several vector operations in parallel. Meanwhile, AVX-512 is incredibly powerful when the workload has enough parallel data to actually use those 512-bit operations. And ARM is no longer just 128-bit NEON either. SVE/SVE2 introduced scalable vectors, while SME/SME2 adds scalable streaming vectors and matrix processing. Apple's newer M4/A18-generation CPUs support SME/SME2, so describing modern Apple Silicon as simply "128-bit SIMD" isn't accurate anymore. The important point is: 128-bit vs 512-bit tells you how much data ONE vector instruction can describe. It does NOT tell you how fast the entire CPU is. AVX-512 can win massively in the right vector-heavy workload. But for general CPU performance, a wider SIMD instruction alone doesn't guarantee a faster CPU. That's how a CPU built around 128-bit NEON can still compete with, or sometimes outperform, a CPU that supports 512-bit AVX-512. SIMD width tells you how wide an instruction can be. Microarchitecture + workload tell you how much of that width actually turns into performance.